1. Field of the Invention
The present invention relates to a semiconductor substrate including doped zones forming respective P-N junctions.
The invention is typically but not exclusively applicable to the field of semiconductor substrates including an embedded or buried layer, generally known as a “buried layer”.
More particularly, the semiconductor substrate forms part of an integrated circuit obtained, for example, by means of technologies that are well known to the skilled person such as CMOS (complementary metal oxide semiconductor), BICMOS (bipolar-CMOS) or BCD (bipolar, CMOS, CMOS).
2. Description of Related Art
In those various types of technologies, embedded doped layers or “buried layers” are often provided within a semiconductor material in order to assume various functions such as a collector for a bipolar transistor, a drain for a vertical transistor, or simply for vertical isolation at depth. Thus, such layers have multiple applications and may, for example, be used to define a triple well, which corresponds to an isolated zone that is capable of receiving a particular polarization. Document U.S. Pat. No. 7,008,836 may be mentioned in this regard; it describes the fabrication of a P-doped triple well, which is a zone defined by two N-wells within a P-doped silicon semiconductor substrate, those two N-wells being connected together at depth by a “buried” N-doped layer. The front face of the substrate is the face on which the active components of the integrated circuit, such as transistors, for example, are positioned.
One of the two N-wells may readily be used in part to form a P-N junction, in contact with the front face of the substrate, with an adjacent P element (for example another P-well). The diode-type nature of that junction is frequently used to isolate the N- and P-wells from each other by polarizing it with a reverse electric field. The relative distance between the N-well and the P-well determines the applicable maximum electric field for proper isolation of those two elements.